www.siliconstandard.com 1 of 7 SS6383(g) 10/07/2004 rev.1.01 1.5a ddr termination regulator features description source and sink current capability of 1.5a low output voltage offset, 20mv high accuracy output voltage at full-load v out adjustable by external resistors low external component count current limit protection thermal protection so-8 package applications mother board graphic cards ddr termination voltage supply - supports the SS6383 linear regulator is designed to provide 1.5a source and sink current while regulating an output voltage to within 25mv. the SS6383 converts voltage supplies ranging from 1.6v to 6v into an output voltage that is set by two external voltage-divider resistors. it provides an excellent voltage source for active termination schemes for high-speed transmission lines such as those seen in high- speed memory buses. the built-in current-limiting in source and sink mode, together with thermal shutdown, provides maximum protection to the SS6383 against fault conditions. typical application circuit ddr1 (1.25v tt ), ddr2 (0.9v tt ), and meets jedec sstl-2 and sstl-3 term. specifications 100k 100pf en + c out 220 f + c in 470 f r 1 100k r2 v in =2.5 v ssm7002 en c1 1 2 4 3 + c cntl 47 f v cntl =3.3 v vin gnd vcntl 8 vout vref vcntl 7 vcntl 6 vcntl 5 SS6383 v out =1.25v this device is available with pb-free lead finish (second-level interconnect) as SS6383gs
www.siliconstandard.com 2 of 7 ordering information pin configuration example: SS6383gstr packing tr: tape and reel package type cs: so-8, commercial so-8 top view vcntl vcntl vcntl vcntl vref gnd vout vin 1 3 4 2 8 6 5 7 absolute maximum ratings supply voltage -0.4v to 7v operating temperature range -40c~85c junction temperature range 125c lead temperature (solder, 10sec) 260c so-8 160c /w thermal resistance ja (assumes no ambient airflow, no heatsink) note1: any stress beyond these absolute maximum ratings may cause permanent damage to the device. 10 /07 /2004 r e v .1 . 01 SS6383(g) gs: so-8, commercial with pb-free lead finish thermal resistance . jc so-8 40c /w test circuit 2.5v/1.8v 1.25v/0.9v v out + c out 10 f vin 1 gnd 2 vcntl 8 vout 4 vref 3 vcntl 7 vcntl 6 vcntl 5 SS6383 3.3v storage temperature range -65c ~150c
www.siliconstandard.com 3 of 7 10 /07 /2004 r e v .1 . 01 SS6383(g) electrical characteristics vcntl=3.3v, vin=2.5v, vref=0.5vin, c out =10f, t a =25c, unless otherwise specified) (note 1) parameter test conditions symbol min. typ. max. unit v in 1.6 2.5/1.8 input voltage (ddr1/2) keep v cntl v in during power on and off sequences v cntl 3.0 3.3 6 v output voltage i out = 0ma v out v ref v output voltage offset i out = 0ma (note 2) v os -20 20 mv i out =0.1ma ~ +1.5a 10 25 load regulation (ddr1/2) i out = 0.1ma ~ -1.5a ?v lor 10 25 mv quiescent current v ref <0.2v, v out = off i q 8 30 a operating current of v cntl no load i cntl 3 10 ma v ref bias current v ref =1.25v 1 a current limit i il 2.1 3 4.5 a thermal protection thermal shutdown temperature 3.3v v cntl 5v t sd 125 150 c thermal shutdown hysteresis guaranteed by design 30 c shutdown specifications output on (v ref =0v 1.25v) 0.8 shutdown threshold output off (v ref =1.25v 0v) 0.2 v not e 1 : specifications are production-tested at t a =25 c. specifications over the -40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical quality controls (sqc). note 2 : v os is the difference between v out and v ref . note 3 : load regulation is measured at constant junction tem perature, using pulse testing with a low duty cycle. note 4 : current limit is measured using a low duty cycle. note 5 : to operate safely, v cntl must always be greater than v in . (note 3) (note 4)
www.siliconstandard.com 4 of 7 10 /07 /2004 r e v .1 . 01 SS6383(g) typical performance characteristics -40 -2 0 0 20 40 60 80 10 0 12 0 0. 30 0. 35 0. 40 0. 45 0. 50 0. 55 v cn t l =3 .3v v in =2 .5v th re sh ol d vo lta g e (v) t e mp er at ur e (c) f i g. 1 t u r n - o n t h r e sho l d v s . t e mp. t e mp era t ure ( c) -40 -2 0 0 20 40 60 80 10 0 12 0 0. 30 0. 35 0. 40 0. 45 0. 50 0. 55 th re sh ol d vo lta g e (v) fi g. 2 t u r n - o n t h r e shol d v s . t e mp v cn t l =5v v in =2.5 v -40 - 20 0 2 0 4 0 6 0 8 0 100 120 0. 0 0. 5 1. 0 1. 5 2. 0 2. 5 3. 0 v cn t l =3.3v, v in =2. 5 v v out =1.25v ou tput vo ltag e off s et (mv) te mpe r ature ( o c) fig . 3 o u tpu t v o l t ag e o ffset v s . t e mp er at ur e v cn t l =3.3v v in =2 .5 v v re f = 1 .25v no lo ad t e mp era t ure (c) so u r ci ng curre nt (a) fig . 4 cu rren t -li m i t (so u r ci ng ) v s . t e mp era t ure -4 0 -20 0 20 40 60 80 100 12 0 0 1 2 3 4 5 v cn t l =3 .3v v in =2 .5v v out =1 .25 v si nk in g curre nt (a) t e mp er at ur e (c) f i g. 5 c u r r e n t - l i m i t ( s i n king ) v s . t e mp er a t ur e -4 0 -20 0 20 40 60 80 100 12 0 0 1 2 3 4 5 v cntl =3 . 3 v v in =2 .5v v out = 1 .2 5v
www.siliconstandard.com 5 of 7 10 /07 /2004 r e v .1 . 01 SS6383(g) typical performance characteristics (continued) fig. 6 output short-circuit (sinking) i out : 1a/div v in =2.5v v cntl =3.3v v ref =1.25v fig. 7 output short-circ uit protection (sourcing) i out : 1a/div v in =2.5v v cntl =3.3v v ref =1.25v fig. 8 transient response at 1.25v tt /1.5a v in =2.5v v cntl =3.3v v ref =1.25v i out : 1a/div v out : 50mv/div fig. 9 transient response at 0.9v tt /1.5a v in =1.8v v cntl =3.3v v ref =0.9v i out : 1a/div v out : 50mv/div block diagram vout - + vout gnd vin control vcntl shutdown shutdown thermal current limit vref
www.siliconstandard.com 6 of 7 10 /07 /2004 r e v .1 . 01 SS6383(g) pin descriptions pin 1: vin - input supply pin - provides power to create the external reference voltage using a resistor divider for regulating v ref and v out . pin 2: gnd - ground pin. pin 3: vref - reference voltage input. pull this pin low to shut the device down. pin 4: vout - output pin. pin 5~8: vcntl - input supply pin - supplies all the internal control circuitry. application information layout consideration the SS6383 is in an so-8 package and is unable to dissipate heat easily when operating with high currents. in order to avoid exceeding the maximum junction temperature, an appropriate area of copper must be used. the large copper area around the v cntl pins can be used to assist the heat dissipation. vias to lead heat into the bottom layer are also recommended. all capacitors should be placed as close to the relative ic pin as possible. fig. 10. top layer fig. 11. bottom layer fig. 12. placement
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 7 of 7 10 /07 /2004 r e v .1 . 01 SS6383(g) physical dimensions (unit: mm) so-8 symbol min max a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 q 0 8 d h e a b a1 c e l q h x 45 gauge plane seating plane 0.25
|
